VLSI CAD Part I: Logic

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  • Orientation
    • In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.
  • Computational Boolean Algebra
    • In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to Boolean algebra.
  • Boolean Representation via BDDs and SAT
    • Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on industrial-scale designs.
  • 2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
    • In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra.
  • Multilevel Factor Extract and Don't Cares
    • You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic.
  • Final Exam
    • There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.

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