System Design Through VERILOG
Week-1:Introduction to Verilog
Week-2:Gate level modelling Week-3:Behavioral modelling I
Week-4:Behavioral modelling II Week-5:Data flow modelling Week-6:Switch level modelling
Week-7:Synthesis of combinational logic using verilog
Week-8:Synthesis of sequential logic using verilog
Week-2:Gate level modelling Week-3:Behavioral modelling I
Week-4:Behavioral modelling II Week-5:Data flow modelling Week-6:Switch level modelling
Week-7:Synthesis of combinational logic using verilog
Week-8:Synthesis of sequential logic using verilog
