Multi-Core Computer Architecture – Storage and Interconnects
Week 1: Fundamentals of instruction pipeline for superscalar processor design
Week 2: Memory hierarchy design, cache memory - fundamentals and basic optimisations
Week 3: Cache memory – advanced optimisations, performance improvement technqiues
Week 4: gem5 simulator – build and run, address translations using TLB and page table
Week 5: DRAM – organisation, access techniques, scheduling algorithms and signal systems.
Week 6: Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7: NoC router – architecture, design, routing algorithms and flow control techniques.
Week 8: Advanced topics in NoC and storage – compression, prefetching, QoS.
Week 2: Memory hierarchy design, cache memory - fundamentals and basic optimisations
Week 3: Cache memory – advanced optimisations, performance improvement technqiues
Week 4: gem5 simulator – build and run, address translations using TLB and page table
Week 5: DRAM – organisation, access techniques, scheduling algorithms and signal systems.
Week 6: Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7: NoC router – architecture, design, routing algorithms and flow control techniques.
Week 8: Advanced topics in NoC and storage – compression, prefetching, QoS.
