Hardware modeling using verilog

Por: Swayam . en: ,

Week 1: Introduction to digital circuit design flow (3 hours)Week 2: Verilog variables, operators and language constructs (2 hours)Week 3: Modeling combinational circuits using Verilog (2 hours)Week 4: Modeling sequential circuits using Verilog (3 hours)Week 5: Verilog test benches and design simulation (2 hours)Week 6: Behavioral versus structural design modeling (2 hours)Week 7: Miscellaneous modeling issues: pipelining, memory, etc. (2 hours)Week 8: Processor design using Verilog (4 hours)

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