Expanded FPGA Training with NIOS II
The complexity of digital logic designs requires understanding of large scale devices such as Field Programmable Gate Arrays (FPGAs) to realize solutions. Implementation in discrete components is nearly impossible to realize and debug due to the growing complexity of solutions. Integration of processor capability into one platform enables reduction in size and conservation of power with improved microelectronic hardware. The focus of this specialization is the practical use of Soft Processors with emphasis on testing and debugging in applications of video.
Hands on bring up of DE10-Lite board with expansion into the use of the VGA output interface is provided. Focus on the use of the NIOS II processor to control Video IP for generation of test pattern output after reviewing the sample test pattern demonstration in Verilog. Review of the manual for the implementation of Video IP for display of signals using the Avalon-ST streaming protocol is covered. Tools for the design of systems are provided which include the System Console and TCL scripts for evaluation of board and processor interfaces with custom project, and an embedded Logic Analyzer for probing of signal values to characterize performance and state transition. A traffic light controller and thunderbird tail lights are used to provide hands-on examples.
Hardware setup and verification for DE10-Lite with VGA monitor output
-Focus on the use of hardware platform with detailed support for key steps necessary to launch solutions from demonstration folders provided by manufacturer of FPGA systems. Examples provided with an emphasis on video. Additional resources are pointed out for access. Peer review assignment evaluates understanding of key concepts in FPGA design software and interaction with TPG and CVO Video IP blocks.
Methods and approaches for testing FPGA designs
-Overview of tools for design verification for functionality and performance. Discussion of system console capabilities using TCL scripts with emphasis on board bring up and processor evaluation. Description of embedded logic analyzer capabilities with triggering for state transition verification and logic operation along with capabilities to store results for data analysis. Brief introduction to external memory evaluation capabilities to be discussed in future modules.
NIOS II IP for Video and Performance Monitoring
-This module covers the use of additional Video IP suite modules with emphasis on the bus interfaces used for streaming along with more test modules that are available in System Console for verification. Introduction to custom IP blocks is provided using TCL and the Custom IP capabilities in the Soft Processor environment of Qsys provided by the Intel development tools for FPGA design.