Expanded FPGA Training with NIOS II
Descripción del Curso
Hands on bring up of DE10-Lite board with expansion into the use of the VGA output interface is provided. Focus on the use of the NIOS II processor to control Video IP for generation of test pattern output after reviewing the sample test pattern demonstration in Verilog. Review of the manual for the implementation of Video IP for display of signals using the Avalon-ST streaming protocol is covered. Tools for the design of systems are provided which include the System Console and TCL scripts for evaluation of board and processor interfaces with custom project, and an embedded Logic Analyzer for probing of signal values to characterize performance and state transition. A traffic light controller and thunderbird tail lights are used to provide hands-on examples.