Testing is an integral part of the VLSI design cycle. With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging. Testing occupies 60-80% time of the design process. A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing. Design for testability (DFT) is a matured domain now, and thus needs to be followed by all the VLSI designers. In this context, the course attempts to expose the students and practitioners to the most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in large quantity.
INTENDED AUDIENCE : Any interested learners
PREREQUISITES : Digital Design / Digital Logic
INDUSTRY SUPPORT : Companies involved in development of VLSI chips
COURSE LAYOUT Week 1:Introduction: Importance, Challenges, Levels of abstraction, Fault Models, Advanced issuesWeek 2:Design for Testability: Introduction, Testability Analysis, DFT Basics, Scan cell design, Scan ArchitectureWeek 3:Design for Testability: Scan design rules, Scan design flow . Fault Simulation: Introduction, Simulation modelsWeek 4:Fault Simulation: Logic simulation, Fault simulationWeek 5:Test Generation: Introduction, Exhaustive testing, Boolean difference, Basic ATPG algorithmsWeek 6:Test Generation: ATPG for non stuck-at faults, Other issues in test generation Built-In-Self-Test: Introduction, BIST design rulesWeek 7:Built-In-Self-Test: Test pattern generation, Output response analysis, Logic BIST architecturesWeek 8:Test Compression: Introduction, Stimulus compressionWeek 9:Test Compression: Stimulus compression, Response compressionWeek 10:Memory Testing: Introduction, RAM fault models, RAM test generationWeek 11:Memory Testing: Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPGWeek 12:Power and Thermal Aware Test: Low power BIST, Thermal aware techniques